VLSI BASED PROJECTS

2014 UPDATED LIST

1. A Novel Reconfigurable Architecture For Generic OFDM Modulator Based On FPGA
2. A Novel Interleaver Design For Multimode Communication In WLAN
3. High-Throughput Programmable Systolic Array  FFT Architecture and FPGA Implementations
4. A Novel Interleaver Design for Multimode Communication in WLAN
5.  A Reconfigurable Overlapping FFT/IFFT Filter for ECG Signal De-noising
6. Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems
7. FPGA based partial reconfigurable fir filter design
8.  Implementation of Canny Edge Detection Algorithm on FPGA and displaying Image through VGA Interface
9. Efficient Architecture Mapping Of Fft/Ifft For Cognitive Radio Networks
10. On the 2×2 DFT-spread Space-Time Block Code CO-OFDM for PDM optical communications
11. Scalable low power FFT/IFFT architecture with dynamic bit width configurability
12. An FPGA-Based Fully Synchronized Design of a Bilateral Filter for Real-Time Image Denoising
13. Novel Architecture for Efficient FPGA Implementation of Elliptic Curve Cryptographic Processor Over GF(2163)
14. Analysis and Implementation of Low-cost FPGABased Digital Pulse-width Modulators
15. Implementation and Evaluation of a High-Performance MIMO Detector for Wireless LAN Systems
16. FPGA Based Implementation of a Double Precision IEEE Floating-Point Adder

IEEE PROJECTS ON FPGA: XILINX ZYNQ BOARD EPP 7000

1. Design and Implementation of FPGA - Digital Based PID Controller
2. An FPGA Implementation of Frequency Output
3. A Review on FPGA Based Pulse Processing System
4. FPGA based partial reconfigurable FIR filter design
5. Implementation of Canny Edge Detection Algorithm on FPGA and displaying Image through VGA Interface
6. Comparative analysis of different hardware decoder architectures for IEEE 802.11ad LDPC code
7. Fault Tolerant Parallel Filters Based on Error Correction Codes
8. Analysis and Implementation of Low-cost FPGA Based Digital Pulse-width Modulators

NETWORK SECURITY & CRYPTOGRAPHIC SCIENCES

1. Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed
2. Efficient Implementation of Reconfigurable Warped Digital Filters With Variable Low-Pass, High-Pass, Bandpass, and Bandstop Responses
3. Off-Chip Memory Encryption and Integrity Protection Based on AES-GCM in Embedded Systems
4. FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area Network
5. High performance scalar multiplication for ECC
6. An efficient FPGA implementation of the Advanced Encryption Standard algorithm
7. A compact 32-Bit AES design for embedded system
8. An Implementation of AES Algorithm Based on FPGA
9. Hardware efficiency comparison Of AES implementations
10. A Novel Architecture for VLSI Implementation of RSA Cryptosystem
11. A FPGA Design of AES Core Architecture for Portable Hard Disk
12. A Novel Stream Cipher with Hash Function for the RFID Device

DIGITAL SIGNAL PROCESSING

1. Low-Complexity Multiplier for GF(2m) Based on All-One Polynomials
2. Low Latency Systolic Montgomery Multiplier for Finite Field Based on Pentanomials
3. CORDIC Designs for Fixed Angle of Rotation
4. CORDIC Based Fast Radix-2 DCT Algorithm
5. Low power and memory efficient FFT architecture using modified CORDIC algorithm
6. CORDIC Designs for Fixed Angle of Rotation
7. A survey of FPGA based Interference cancellation architectures for biomedical signals
8. Optimized FIR filters for digital pulse compression of biphase codes with low sidelobes
9. Design and Implementation of Adaptive filtering algorithm for Noise Cancellation in speech signal on FPGA
10. Implementation of generalized dft on field programmable gate array
11. Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA Implementation
12. Distributed Arithmetic LMS Adaptive Filter Implementation without Look-Up Table
13. Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm
14. Fully Parallel and Fully Serial architecture for realization of high speed FIR Filters with FPGA's
15. A Dynamic Partial Reconfigurable FIR Filter Architecture
16. Hardware Implementation of Discrete Fourier Transform and its Inverse Using Floating Point Numbers
17. Implementation of Adaptive FIR Filter for Pulse Doppler Radar
18. FPGA Implementation of an Adaptive Filter Robust to Impulsive Noise: Two Approaches
19. FPGA Implementation of Digital Up/Down Convertor for WCDMA System
20. Design and FPGA Implementation of Linear FIR Low-pass Filter Based on Kaiser Window Function
21. FPGA Implementation of Adaptive LMS Filter
22. An event-driven FIR filter: design and Implementation
23. Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm

ARITHMETIC CORE AND DIGITAL ELECTRONICS

1. Low-Power and Area-Efficient Carry Select Adder
2. Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection
3. Design and implementation of demodulation technique with complex dpll using cordic algorithm
4. A New Approach for High Performance and Efficient Design of CORDIC Processor
5. Design of Plural-Multiplier Based on CORDIC Algorithm for FFT Application
6. Hardware Efficient Architecture for Generating Sine/Cosine Waves
7. FPGA Design of a Fast 32-bit Floating Point Multiplier Unit
8. Design & Implementation of Floating point ALU
9. A FPGA IEEE-754-2008 DECIMAL64 FLOATING-POINT ADDER/SUBTRACTOR
10. FPGA Implementation of Sine and Cosine Value Generators using Cordic Algorithm for Satellite Attitude Determination and Calculators
11. Design and Implementation of CORDIC Processor for Complex DPLL
12. Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection
13. FPGA Implementation of a chaotic oscillator using RK4 method
14. An Efficient Implementation of Floating Point Multiplier

DIGITAL COMMUNICATIONS AND INFORMATION THEORY

1. Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes
2. Reconfigurable FFT using CORDIC based architecture for MIMO-OFDM receivers
3. Speed optimization of a FPGA based modified viterbi decoder
4. Faulty Node Detection in Distributed Systems Using BCH Code
5. Optimizing Chien Search Usage in the BCH Decoder for High Error Rate Transmission
6. BPSK System on Spartan 3E FPGA
7. FPGA Implementation of Encoder for (15, k) Binary BCH Code Using VHDL and Performance Comparison for Multiple Error Correction Control
8. Design of a Mixed-Signal Cartesian Feedback Loop for a Low Power Zero-IF WCDMA Transmitter
9. Design and implementation of demodulation technique with complex dpll using cordic algorithm
10. Implementation of generalized dft on field programmable gate array
11. Design and Implementation of Reed Solomon Decoder for 802.16 Network using FPGA
12. Hardware Implementation of Discrete Fourier Transform and its Inverse Using Floating Point Numbers
13. Implementation of Adaptive FIR Filter for Pulse Doppler Radar
14. FPGA Implementation of Modified Architecture for Adaptive Viterbi Decoder
15. An Efficient All-Digital Phase-Locked Loop with Input Fault Detection
16. A Novel Hardware-Based All-Digital Phase-Locked Loop Applied to Grid-Connected Power Converters
17. Mixed Cartesian Feedback for Zero-IF WCDMA Transmitter
18. FPGA Implementation of Digital Up/Down Convertor for WCDMA System
19. Analysis of 32-bit Fault Tolerant ALU Methods

DIGITAL IMAGE PROCESSING 

1. A Low-Cost VLSI Implementation for Efficient Removal of Impulse Noise
2. An FPGA-Based Hardware Implementation of Configurable Pixel-Level Color Image Fusion
3. Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWT
4. HD Resolution Intra Prediction Architecture for H.264 Decoder

BUS PROTOCOLS AND SYSTEM ON CHIP

1. FPGA based implementation of a double precision IEEE floating-point adder
2. Design and Functional Verification of I2C Master Core using OVM